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If no wall segments have failed, a check is made to see if the re wall has been overtopped, and, if so, the balance of oil volume larger than the patio capacity is considered to be released Finally, a summation of oil spilled out of all the patios onto the facilities is made, and the revetment (and its associated outer re wall) is checked to see whether failure occurred, in which case all the oil spilled onto the facility is considered to be released off site If the revetment has not failed, a check is made for overtopping, in which case the balance of oil greater than the site capacity is considered to have been spilled off site At the end, a histogram of oil.

Because a large part of the reversing process often takes place inside a debugger, it is sometimes beneficial to incorporate special code in the program that prevents or complicates the process of stepping through the program and placing breakpoints in it. Antidebugger techniques are particularly effective when combined with code encryption because encrypting the program forces reversers to run it inside a debugger in order to allow the program to decrypt itself. As discussed earlier, it is sometimes possible to unpack programs automatically using unpackers without running them, but it is possible to create a code encryption scheme that make it impossible to automatically unpack the encrypted executable. Throughout the years there have been dozens of antidebugger tricks, but it s important to realize that they are almost always platform-specific and depend heavily on the specific operating system on which the software is running. Antidebugger tricks are also risky, because they can sometimes generate false positives and cause the program to malfunction even though no debugger is present. The same is not true for code obfuscation, in which the program typically grows in footprint or decreases in runtime performance, but the costs can be calculated in advance, and there are no unpredictable side effects. The rest of this section explains some debugger basics which are necessary for understanding these antidebugger tricks, and proceeds to discuss specific antidebugging tricks that are reasonably effective and are compatible with NTbased operating systems.

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To understand some of the antidebugger tricks that follow a basic understanding of how debuggers work is required. Without going into the details of how user-mode and kernel-mode debuggers attach into their targets, let s discuss how debuggers pause and control their debugees. When a user sets a breakpoint on an instruction, the debugger usually replaces that instruction with an int 3 instruction. The int 3 instruction is a special breakpoint interrupt that notifies the debugger that a breakpoint has been reached. Once the debugger is notified that the int 3 has been reached, it replaces the int 3 with the original instruction from the program and freezes the program so that the operator (typically a software developer) can inspect its state. An alternative method of placing breakpoints in the program is to use hardware breakpoints. A hardware breakpoint is a breakpoint that the processor itself manages. Hardware breakpoints don t modify anything in the target program the processor simply knows to break when a specific memory address is accessed. Such a memory address could either be a data address accessed by

100 90 80 PROBABILITY (%) 70 60 50 40 30 20 10 0 30 40 50 60 TANK INVENTRY (%) TOTAL CAPACITY 70 80 RATIO A RATIO B RATIO C

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the program (such as the address of a certain variable) or it could simply be a code address within the executable (in which case the hardware breakpoint provides equivalent functionality to a software breakpoint). Once a breakpoint is hit, users typically step through the code in order to analyze it. Stepping through code means that each instruction is executed individually and that control is returned to the debugger after each program instruction is executed. Single-stepping is implemented on IA-32 processors using the processor s trap flag (TF) in the EFLAGS register. When the trap flag is enabled, the processor generates an interrupt after every instruction that is executed. In this case the interrupt is interrupt number 1, which is the singlestep interrupt.

Figure 22.19 Site production records expressed as probability of proportion of tank inventory in use. (T. W. Lambe & Associates 1982, 1989, reproduced with permission.)

a south-facing coast with an easterly breeze; a north-facing coast with a westerly breeze; an east-facing coast with a northerly breeze; or a west-facing coast with a southerly breeze

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